Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5

A developer has publicly shared a version of the Project Oberon operating system running on RISC-V hardware, replacing the original RISC-5 architecture. This development demonstrates the OS’s adaptability to new hardware platforms, marking a significant step in its portability and open-source hardware efforts.

The project was shared via a Show HN post, where the developer showcased a working version of Oberon on a RISC-V processor. The port involves adapting the system’s kernel and hardware interface layers to support RISC-V, a modern open-source instruction set architecture (ISA) gaining popularity in academia and industry.

According to the developer, the port is in early stages but functional enough to run core system components. The developer also provided a brief demonstration, showing the system booting and basic operations on RISC-V hardware, which was previously only supported on RISC-5 architecture.

Potential Impact of RISC-V Port on Oberon Ecosystem

This port could significantly extend the lifespan and relevance of the Project Oberon operating system by making it compatible with RISC-V hardware. RISC-V’s open-source nature allows for more customizable, affordable, and accessible hardware platforms, which could facilitate broader adoption of Oberon in academic and hobbyist communities.

Moreover, demonstrating that Oberon can run on RISC-V challenges the notion that legacy systems are limited to specific architectures, highlighting the OS’s modular design and portability. This could inspire further porting efforts and development of Oberon-based systems on diverse hardware.

Background on Project Oberon and RISC-V Compatibility Efforts

Project Oberon, developed by Niklaus Wirth and colleagues at ETH Zurich, is a minimalist operating system and programming environment designed for simplicity and efficiency. Historically, it was built for the RISC-5 architecture, a proprietary processor used in the original Oberon hardware.

In recent years, RISC-V has emerged as a prominent open-source ISA, with growing support from academia, industry, and hobbyists. While there have been various efforts to port operating systems like Linux and BSD to RISC-V, porting specialized systems like Oberon has remained limited.

This latest development marks the first publicly shared attempt to adapt Oberon to RISC-V, signaling a potential shift toward broader hardware compatibility for the system.

“This is an initial version, but it demonstrates that Oberon can run on RISC-V hardware with some modifications. It’s a proof of concept for future development.”

— The developer behind the port

Extent of System Functionality and Future Support

It is not yet clear how fully functional the port is beyond basic booting and core operations. Details on peripheral support, stability, and performance remain unconfirmed, and ongoing development is likely required to reach production-level stability.

Additionally, the timeline for official support, community involvement, or further enhancements has not been disclosed by the developer.

Next Steps for RISC-V Oberon Port Development

The developer plans to continue refining the port, adding support for more hardware features and improving stability. Community feedback and contributions could accelerate development, potentially leading to a more complete version suitable for wider testing.

Further demonstrations and detailed documentation are expected to follow, which will clarify the port’s capabilities and encourage other developers to experiment with Oberon on RISC-V hardware.

Key Questions

What is Project Oberon?

Project Oberon is a minimalist operating system and programming environment designed for simplicity and efficiency, originally developed at ETH Zurich for the RISC-5 architecture.

Why is porting Oberon to RISC-V significant?

Porting Oberon to RISC-V demonstrates its adaptability to open-source hardware, potentially broadening its user base and enabling educational and hobbyist use on affordable, customizable platforms.

Is the RISC-V port fully functional?

Currently, the port is in early stages and primarily demonstrates basic booting and core system operation. Full hardware support and stability are still under development.

Could this lead to wider adoption of Oberon?

If further development succeeds, it could encourage more experimentation and adoption within academic and open-source communities, especially given RISC-V’s growing popularity.

Will this affect the future of RISC-5 hardware?

There is no indication that this port will impact RISC-5 hardware directly; instead, it highlights the potential for Oberon to run on diverse architectures.

Source: hn